In DRAMS, the memory cells consisting substantially of capacitors are connected to bit lines so as to transmit a data value to be read out from a memory cell or a data value to be read into a memory cell. On the reading out of a memory cell, an access transistor that is connected with the capacitor of a memory cell is connected through by the activation of a word line, and the charge condition stored in the capacitor is applied to the bit line. Subsequently, the weak signal emanating from the capacitor is amplified by a read amplifier. The read amplifier comprises complementary signal inputs. The bit lines connected to these signal inputs are referred to as bit line and complementary bit line.
In today's DRAMS, the read amplifiers are, as a rule, used as divided parts so as to safe chip space. In so doing, a read amplifier is used both during the reading out of a memory cell positioned at the left and a memory cell positioned at the right along a bit line next to the read amplifier.
Prior to the reading out of the memory cells, the corresponding bit line sections, i.e. the corresponding sections of the non-complementary bit line and of the complementary bit line, are, by so-called precharge/equalize circuits that are connected with the bit lines, precharged to the same potential, which corresponds to half the voltage of a bit line in the h-state (=VBLH/2). This ensures that no differences occur prior to the reading out between the potential of a section of the bit line and the section of the complementary bit line assigned thereto, which might superimpose or adulterate the small amount of charge transferred by the capacitor of a memory cell to the bit line during reading out. Directly prior to the reading out of the memory cells are the precharge/equalize circuits which are connected to the bit line sections that are adapted to be connected with the memory cell to be read out and with the read amplifier switched off.
Known DRAMS moreover comprise isolation transistors which serve to decouple the read amplifier during the reading out of the cells from the side that is not to be read out.
With known DRAMs, bias voltages are applied outside the read and write cycles to the gate terminals of the isolation transistors which, as a rule, consist of two NMOS-FETs, the source-drain paths of which are adapted to interrupt the corresponding bit line sections, said bias voltages corresponding to the voltage (VINT) generated internally on the DRAM chip. Directly prior to the reading out of a memory cell is the one side of the read amplifier that could be connected with the memory cell that is not to be read out coupled off the bit lines by the gate terminals of the isolation transistors positioned on this side of the read amplifier being put to mass potential. Simultaneously, the other side of the read amplifier is coupled in an improved manner by the gate voltage that is applied to the gate terminals of the isolation transistors positioned on the other side of the read amplifier being slightly increased from its initial value VINT to a voltage value VPP.
The actual reading out of the memory cell is initiated shortly thereafter by appropriate word line signals connecting through the access transistors that are connected with the memory capacitors. Subsequently, appropriate activating voltages are applied to the read amplifier, whereupon the read amplifier amplifies the potential differences transferred from the memory capacitors to the two bit line sections.
In the case of previous DRAMs, the voltage (VEQL) applied to the gate terminals of the MOS-FETs of the precharge/equalize circuit, which resulted in the activation of the precharge-/equalize circuits and in the precharging of the corresponding bit line sections prior to the actual reading out and/or writing in of a memory cell, corresponded to the internal chip voltage VINT applied to the isolation transistors prior to the reading out/writing in of a memory cell. This was an efficient and simple solution since VINT is available practically everywhere on the chip and need not be generated expensively by a charge pump circuit.
However, this simple solution involves a number of problems in the case of future cell field architectures of DRAMs which have to do with reduced operating voltages so as to realize low power consumption of the memory chip.
Thus, in the case of the reduced operating voltage (VINT), the time up to the complete precharging of the bit lines would become too long and might therefore violate predetermined component specifications. This could only be counteracted by a pumped voltage which would, for instance, be generated by a charge pump circuit from the internal chip voltage (VINT), being used for triggering the precharge/equalize circuits. Since the entire capacity of the line (EQL line) positioned along the bit lines for triggering the numerous precharge/equalize circuits is very large, the increased voltage (VEQL) would result in a distinctly increased power consumption of the DRAM during the read out process vis-à-vis a DRAM that can do without pumped voltage VEQL. A high power consumption results in particular also from the fact that the memory cell contents regularly have to be refreshed with the DRAM, so that an increased power consumption results even if the device is not active. This counteracts the reduction of power consumption originally to be achieved by the reduction of the operating voltage of the chip and has a negative effect in particular with battery-operated devices such as PDAs or mobile phones incorporating the DRAM. To achieve a battery lifetime as long as possible, the power consumption will have to be reduced as much as possible with such devices.